//////////////////////////////////////////////////////////////////////////////// // Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. //////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version : 8.1i // \ \ Application : xaw2verilog // / / Filename : ClockModule.v // /___/ /\ Timestamp : 11/14/2006 16:24:35 // \ \ / \ // \___\/\___\ // //Command: xaw2verilog -intstyle C:/DESIGNS/FPGA/Custom_Libera/ClockModule.xaw -st ClockModule.v //Design Name: ClockModule //Device: xc2vp30-6ff1152 // // Module ClockModule // Generated by Xilinx Architecture Wizard // Written for synthesis tool: XST `timescale 1ns / 1ps module ClockModule(CLKIN_N_IN, CLKIN_P_IN, RST_IN, CLKIN_IBUFGDS_OUT, CLK0_OUT, LOCKED_OUT); input CLKIN_N_IN; input CLKIN_P_IN; input RST_IN; output CLKIN_IBUFGDS_OUT; output CLK0_OUT; output LOCKED_OUT; wire CLKFB_IN; wire CLKIN_IBUFGDS; wire CLK0_BUF; wire GND1; assign GND1 = 0; assign CLKIN_IBUFGDS_OUT = CLKIN_IBUFGDS; assign CLK0_OUT = CLKFB_IN; IBUFGDS CLKIN_IBUFGDS_INST (.I(CLKIN_P_IN), .IB(CLKIN_N_IN), .O(CLKIN_IBUFGDS)); BUFG CLK0_BUFG_INST (.I(CLK0_BUF), .O(CLKFB_IN)); DCM DCM_INST (.CLKFB(CLKFB_IN), .CLKIN(CLKIN_IBUFGDS), .DSSEN(GND1), .PSCLK(GND1), .PSEN(GND1), .PSINCDEC(GND1), .RST(RST_IN), .CLKDV(), .CLKFX(), .CLKFX180(), .CLK0(CLK0_BUF), .CLK2X(), .CLK2X180(), .CLK90(), .CLK180(), .CLK270(), .LOCKED(LOCKED_OUT), .PSDONE(), .STATUS()); defparam DCM_INST.CLK_FEEDBACK = "1X"; defparam DCM_INST.CLKDV_DIVIDE = 2.000000; defparam DCM_INST.CLKFX_DIVIDE = 1; defparam DCM_INST.CLKFX_MULTIPLY = 4; defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; defparam DCM_INST.CLKIN_PERIOD = 8.000000; defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; defparam DCM_INST.FACTORY_JF = 16'hC080; defparam DCM_INST.PHASE_SHIFT = 0; defparam DCM_INST.STARTUP_WAIT = "FALSE"; endmodule